A. Field of Invention
The present invention pertains generally to fabrication of semiconductors and more particularly fabrication of integrated circuit devices using a composite dielectric layer.
B. Description of the Background
Spin-on polymers such as polyimides are widely recognized as excellent dielectric materials for use in fabricating multi-level interconnects. Although these polymers perform an excellent job of planarizing underlying topography, the polymer layers are generally found to have low-yield strength relative to inorganic dielectrics and poor dry etch selectivity to commonly used photolithographic masking materials. As a result, highly stressed conductor materials, which have a number of advantageous features, cannot be used in combination with spin-on polymers.
Additionally, when spin-on polymers are placed over a varying topography, feature dependent thickness variations result. In other words, although the upper surface of the polymer layer is planarized, the depth of the polymer layer varies in accordance with the height of the underlying structures. These variations greatly complicate the etching of vias, i.e., vertical openings that allow the connection of conductors between multiple layers. Vias over thin polymer regions must be capable of sustaining long etches without creating unwanted connections to underlying areas while the vias in the thicker polymer regions are being etched. Generally, this problem is avoided by requiring the via features to be internal to the underlying metal features to which the contact is being made. In other words, the vias, or openings, must be fully enclosed by underlying metal features so that during the process of etching the polymer layer, over-etching can be achieved without damaging the underlying structure since the polymer etcher will not etch the metal feature. This requires that dogbones, i.e., enlarged metal features, be employed to ensure full vertical registration of the vias with the metal features. However, dogbones severally limit the density of circuitry that can be achieved in the integrated circuit device.
Fabrication of highly dense, multi-level interconnections necessitates the ability to planarize underlying topography so that submicron etching can be achieved with high fidelity. In other words, the flat surface of the semiconductor layer facilitates detailed masking at a submicron level. Additionally, the fabrication of highly dense, multi-level interconnection requires the capability of vias to be external relative to the underlying metal features to which contact is to be made. In other words, the vias, or openings, can extend over the edges underlying feature. These characteristics have not been achieved by prior art devices.